The present invention relates generally to the fabrication of semiconductor chip packages, and more particularly, to ball grid array (BGA) packages having reduced warpage and enhanced structural strength.
Ball grid array is an advanced type of integrated circuit packaging technology which is characterized by the use of a substrate whose upper surface is mounted with a semiconductor chip and whose lower surface is mounted with a grid array of solder balls. During a surface mount technology process, for example, the BGA package can be mechanically bonded and electrically coupled to a printed circuit board (PCB) by means of these solder balls.
Flip chip ball grid array is a more advanced type of BGA technology that uses flip chip technology in mounting the active side of the chip in an upside-down manner over the substrate and bonded to the same by means of a plurality of solder bumps attached to input/output pads thereon. FIG. 1 shows a cross-sectional view of a conventional semi-finished flip chip package. Flip chip package 2 includes a chip 4 having an upper surface 6 and a lower surface 8 opposite the upper surface 6. A set of solder bumps 10 is connected to contact pads (not shown) on the lower surface 8 of chip 4. Chip 4 is secured to a substrate 12 underlying chip 4. Solder bumps 10 are attached to contact pads (not shown) on an upper surface of substrate 12. An underfill 14 may be filled between chip 4 and substrate 12 to stiffen the flip chip package 2 and protect chip 4 from flexural damage. A set of solder balls 16 may be secured to contact pads (not shown) on a lower surface of substrate 12. Solder balls 16 may also be secured to contact pads (not shown) on a printed circuit board (PCB) substrate 18.
The flip chip package 2 may also include a heat spreader 20 and stiffener 22 for preventing excess warpage of the package and heat dissipation. Heat spreader 20 is mounted on top of chip 4 to dissipate heat generated by chip 4 and to counter-balance the forces exerted by the thermal expansion mismatches between at least the chip 4 and the substrate 12. The conventional flip chip package 2 may also include a thermal interface material (TIM) 26 disposed between chip 4 and heat spreader 20 for transferring the heat generated by chip 4 to heat spreader 20.
The chip 4 and substrate 12 are usually formed of different materials having mismatched coefficients of thermal expansion (CTE). As a result, the chip 4 and substrate 12 experience significantly different dimensional changes during thermal and mechanical stress cycles that create significant thermally-induced stresses in the electrical connections between the chip and the substrate. These high thermal stresses and warpage not only lead to delamination in the low-k dielectric layers in the chip 4, but also cause solder bump cracks leading to failure, thereby degrading the long term operating reliability of the flip chip BGA package. Although stiffeners and heat spreaders limit warpage to a certain degree, they do not entirely eliminate the problem.
As the trend in the industry is to use extreme low dielectric constant (ELK) materials for the dielectric layers in the next generation of interconnect structures, such as semiconductor chips, the ELK films being weaker and less dense than ordinary low-k dielectric films, the effect of a mismatch in the CTE between the chip and the substrate becomes even more pronounced.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved BGA package that addresses the above-discussed issues.